Andre Adrian, DL1ADR
version: 2026-06-07
The words microprocessor, microcomputer and microcontroller are
related, but describe different kinds of "micro". First, micro is
another word for Large Scale Integration (LSI) computing devices
that appeared in the 1970s. One early example is the "Calculator-on-a-Chip"
Mostek MK6010. This IC contained the CPU, ROM, RAM, IO in one
housing and is a mask-programmed
microcontroller by todays wording. The Zilog Z80 and MOS
Technology 6502 are examples of microprocessors, that is only the
CPU is in the IC, ROM, RAM, IO are external. There was always a
limit of maximum number of transistor functions on a IC. Therefore
"CPU only" microprocessors have more computing power then the
microcontrollers of the same vintage. A microcomputer is the final
product. Be it a game console like Atari 2600, a home computer
like Commodore C64 or a personal computer (PC) like IBM PC.
This web page describes a 8052 microcontroller computer. The Intel 8048 or MCS-48 was first released in 1976. The Magnavox Odyssey 2 game console from 1978 used the 8048 microcontroller instead of a microprocessor. The Intel 8051 or MCS-51 was the more powerful follow-on and first released in 1980. I use the Atmel AT89S52, a microcontroller with Flash memory as ROM. The classic 8048 was mask programmed. The 8748 has EPROM.
The 8052 microcontroller RAM has a small size of 256 bytes. The
8052 allows external program and read/write memory. An external 32
KByte SRAM allows program download thru the build-in UART (serial
port). An UART-to-USB bridge with CP2101 or FT232 completes the
connection to the host computer.
There is discussion about "the first microprocessor" and there is
discussion about "the first microcontroller". The Intel 8080 had
real impact on the market, think of S100 bus and CP/M operating
system, earlier microprocessors had not. The first
microcontrollers had little impact. The german company Olympia
produced the CP-3F, the
german company Nixdorf the NCF1.
Other microcontrollers are SGS-Ates
M380 and General Instruments LP8000. The most prominent of
this bunch was Fairchild F8.
There was a dispute between Olympia (AEG) and Fairchild about "who
stole from whom". Instead of a court battle, both
parties made a license agreement. The Fairchild F8 was, like
the CP-3F and the others, a two chip microcontroller. The second
chip contains the program counter (PC), ROM and IO. The first chip
contains the CPU and "scratchpad" RAM. The Mostek MK3870 combined
both F8 chips into one. There was a mask-programmed version like
the MK3870/42 with 4KByte ROM and 64 Bytes RAM. The MK38P70 was
for development. A "real" EPROM is placed on top of the MK38P70:
The Mostek MK3870 can not use external ROM or RAM. The Intel
MCS-48 and MCS-51 range of microcontrollers can. There are
ROM-less versions like the 8040 (MCS-48) and the 8032 (MCS-51).
The Intel microcontrollers are called "Harvard
architecture", that is separate program and data memory. In
my opinion, there is no "real" Harvard architecture. You can
combine /PSEN and /RD CPU outputs to use external RAM for program
AND data memory.
The Fairchild F8 or Mostek MK3850 were used in one of the first
chess computers, the CompuChess
from 1977. This time, the firmware (ROM program) was stolen by Novag
Chess Champion MK1. See the case Data
Cash Systems v. JS&A. A friend of mine had the Novag MK1
chess computer. It played horrible chess ...
The CompuChess binary file is 32014-4950_cmcsi_staid.u3. The
hardware was 2 KByte ROM, 256 Byte RAM controlled by MK3853 and 64
Byte Scratchpad RAM. My idea to run CompuChess on 38P70 is not
working. The 64 Bytes scratchpad RAM shall be enough for a pocket
calculator program. Traditionally this is done in BCD arithmetic
to avoid binary to decimal conversion. The simulator MAME can
execute the CompuChess program with the CompuChess
MAME driver.
Ronald Dekker build a tiny
80(C)32 BASIC board. The 8032 is a ROM-less MCS-51 variant.
I use the AT89S52 with 8KByte ROM. I want to port the monZ80
monitor (BIOS) from the Z80
blinkenlights computer to MCS-51 microcontrollers. Then I
want to run MCS BASIC-52 from 1985. This late BASIC has
one-dimensional DIM, 6-bytes BCD floating point numbers and
IF-THEN-ELSE.
The number of integrated circuits or "chips" is small. The
CPU/ROM/IO AT89S52, the RAM AS6C62256, a low power 32 KByte SRAM,
and two glue chips 74HC00 and 74HC573. The NAND 74HC00 combines
the /PSEN and /RD output of the CPU to create a "von
Neumann" computer architecture with combined program and
data memory. The octal latch 74HC573 de-multiplexes data-bus and
lower address-bus for the RAM. Last but not least a ready-made PCB
with UART-to-USB bridge is used.
The +5V voltage supply (VCC) for the 8052 computer runs thru the
UART-to-USB bridge. The capacitor C1 is placed next to U1, C2 next
to U2 and so on. The NAND gates U4A and U4B can be used for
additional Chip Select for another 32 KByte RAM or another ROM.
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A "NOP tester" is a simple set-up to test the CPU. The
traditional schematic wires the NOP opcode to the databus,
connects a clock source and uses a Logic Analyzer to check
the CPU signals like memory-read, memory-write.
For the AT89S52 I use "External access", that is pin /EA=GND. The
databus is wired to opcode 74h, the "MOV A,#74h" opcode. The
quartz and the reset push button are wired as in the 4-chips 8052
computer above.
The "MOV A,#74h" has a length of 2 bytes, first for opcode,
second for immediate value. The duration is one cycle. A cycle is
12 oscillator clocks or two ALE cycles. The following "Read cycle
Timing" diagramm is from the Intel 8051 Single-Chip Microcomputer
Architectural Specification.
The first Logic Analyzer screenshot shows the details of MCS-51
code memory opcode fetch. The Address Latch Enable (ALE) signals
if the AD-bus carries address-bus (ALE=1) or data-bus (ALE=0)
information. In detail, the ALE falling edge, the transition from
1 to 0, signals valid address.
At the rising edge of /PSEN the value on the AD-bus is copied into
the CPU to the instruction decoder (first byte) or A register
(second byte).
The second Logic Analyzer screenshot shows the "memory walk" with
a longer duration. The AD-bus lines AD0, AD1, AD3 are pulled low
(logic 0, GND). If the AD-bus is not emitting high (logic 1, VCC)
in the address output phase, the value is low. The AD-bus lines
AD2, AD4, AD5 are pulled high. If we consider the differences
between pull low and pull high, we can see that the CPU emits
increasing PC values.
